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1 Mbit SPI Serial Flash
A Microchip Technology Company
SST25VF010A
Data Sheet
Product Identification
Table 2: Product Identification
Address
Data
Manufacturer’s ID
Device ID
SST25VF010A
00000H
00001H
BFH
49H
T2.0 25081
Memory Organization
The SST25VF010A SuperFlash memory array is organized in 4 KByte sectors with 32 KByte overlay
blocks.
Device Operation
The SST25VF010A is accessed through the SPI (Serial Peripheral Interface) bus compatible protocol.
The SPI bus consist of four control lines; Chip Enable (CE#) is used to select the device, and data is
accessed through the Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK).
The SST25VF010A supports both Mode 0 (0,0) and Mode 3 (1,1) of SPI bus operations. The difference
between the two modes, as shown in Figure 2, is the state of the SCK signal when the bus master is in
Stand-by mode and no data is being transferred. The SCK signal is low for Mode 0 and SCK signal is
high for Mode 3. For both modes, the Serial Data In (SI) is sampled at the rising edge of the SCK clock
signal and the Serial Data Output (SO) is driven after the falling edge of the SCK clock signal.
CE#
MODE 3
MODE 3
SCK
SI
MODE 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
DON T CAR E
MODE 0
SO
MSB
HIGH IMPEDANCE
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB
1265 F02.0
Figure 2: SPI Protocol
?2011 Silicon Storage Technology, Inc.
5
S725081A
10/11
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